Title:
スタックパッケージ及びその製造方法
Document Type and Number:
Japanese Patent JP4294161
Kind Code:
B2
Abstract:
The present invention relates to a stack package, as well as a method for fabricating the same, the stack package includes at least two semiconductor chips disposed up and down. Bonding pads are formed in the respective semiconductor chips along a center line. Inner leads of a first lead frame and a second lead frame are attached to bonding pad-disposed faces of the respective semiconductor chips. The inner lead of each lead frame is electrically connected to its corresponding bonding pad by means of metal wires. The inner lead of the first lead frame is also electrically connected to the second lead frame. The entire structure is molded with an epoxy compound so as to expose a connecting part between the first and second lead frames and an outer lead of the second lead frame.
Inventors:
Park Akine
Park Chang Bin
Lee
Shirakichi
Cui Lun Hana
Park Chang Bin
Lee
Shirakichi
Cui Lun Hana
Application Number:
JP13482799A
Publication Date:
July 08, 2009
Filing Date:
May 14, 1999
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H01L21/56; H01L23/28; H01L23/10; H01L23/495; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP7058281A | ||||
| JP9246465A | ||||
| JP4284664A | ||||
| JP4067662A | ||||
| JP7226478A |
Attorney, Agent or Firm:
Kyosei International Patent Office