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Title:
STACKED SWITCHING CIRCUIT
Document Type and Number:
Japanese Patent JPS5966226
Kind Code:
A
Abstract:

PURPOSE: To attain reduction in the chip size and to speed up the response speed by providing a discharge circuit comprising an I2L circuit to a lower-stage switching circuit of a stacked switching circuit comprising an I2L circuit.

CONSTITUTION: The upper-stage switching SW circuit 11 comprising a constant current source 10 and the I2L cicuit and the lower-stage SW circuit 12 are provided between a power supply Vcc and GND. The base of a common emitter SW transistor(TR)Q11 of the circuit 12 is driven with an output current IB of the circuit 11. A discharge circuit 20 comprising an injection TRQ21 and a multi- collector TRQ22 discharges a charge of a capacitor C1 between the base and the emitter of the TRQ11. When a control signal having L level is inputted to an input terminal T1, the TRQ11 of the circuit 12 turns on and a TRQ13 turns off. When the signal at the terminal T1 changes to H level, the TRQ12 turns off and the charge of the capacitor C1 is discharged via the circuit 20, and the switching time is reduced.


Inventors:
FURUHATA MAKOTO
HOSHINO MASAKAZU
Application Number:
JP17617482A
Publication Date:
April 14, 1984
Filing Date:
October 08, 1982
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
International Classes:
H03K17/60; H03K19/091; (IPC1-7): H03K17/60
Attorney, Agent or Firm:
Toshiyuki Usuda



 
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