Title:
START-STOP SYNCHRONOUS COMMUNICATION EQUIPMENT
Document Type and Number:
Japanese Patent JP2834094
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the load of CPU concerning communication error processing and the burden of a user with several settings and to remarkably reduce time for resending in generating a communication error.
SOLUTION: UART 13A is provided with an input/output control circuit 137 switching the input of communication data DS and the output of communication error information EI in response to the supply of a reception finishing signal RE and an error information transmission shift register 136 transmitting communication error information EI to the circuit 137 by synchronizing with a reception clock CKR, and UART 23A is provided with an input/output control circuit 237 switching the output of communication data DS and the input of communication error information EI in response to the supply of a transmission finishing signal TE and an error information receiving shift register 136 retransmission request signal RT to the register 236 by synchronizing with a transmission clock CKT.
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Inventors:
KANAMORI SUMIKO
Application Number:
JP22233896A
Publication Date:
December 09, 1998
Filing Date:
August 23, 1996
Export Citation:
Assignee:
KYUSHU NIPPON DENKI KK
International Classes:
H04L1/16; H04L7/04; H04L25/40; H04L29/08; (IPC1-7): H04L29/08; H04L1/16; H04L7/04; H04L25/40
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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