Title:
State machine circuit
Document Type and Number:
Japanese Patent JP5977209
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To achieve the high speed operation of a state machine circuit by independently and simultaneously controlling a plurality of control object circuit groups for executing pipeline processing.SOLUTION: A state machine circuit includes a plurality of control basic circuits for controlling a plurality of control object circuit groups, and for mutually transferring/receiving a flag signal. The control basic circuit includes: a program memory for preliminarily storing the output pattern of a control signal and the flag pattern of the flag signal; and a selector for selecting either the result of matching between a signal output from the control object circuit group and the output pattern or the result of matching between the flag signal output from the other control basic circuit and the flag pattern. The state machine circuit is configured to output at least either the control signal or the flag signal from the program memory on the basis of the output of the selector.
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Inventors:
Ayaka Hatta
Nobuyuki Tanaka
Satoshi Shigematsu
Nobuyuki Tanaka
Satoshi Shigematsu
Application Number:
JP2013149750A
Publication Date:
August 24, 2016
Filing Date:
July 18, 2013
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06F9/38; G05B19/045
Domestic Patent References:
| JP2011525008A | ||||
| JP2008250987A | ||||
| JP2007141084A | ||||
| JP2005527042A | ||||
| JP2004054761A | ||||
| JP11053216A | ||||
| JP7006094A | ||||
| JP5216657A | ||||
| JP3017780A | ||||
| JP62171032A |
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Yuzo Koike
Shigeki Yamakawa
Yuzo Koike