Title:
STATIC MEMORY CELL
Document Type and Number:
Japanese Patent JP2689940
Kind Code:
B2
Abstract:
PURPOSE: To stabilize the operation of a memory cell by forming a thin film transistor in J-shaped planar pattern, forming a heavily doped P+ region similar to the drain region of TFT at the J-shaped detouring part and providing a node capacity forming region, thereby adding an effective capacitance without requiring any additional process.
CONSTITUTION: TFT active layer polysilicon 11, 11a is formed in J-shaped planar pattern. A source region 12 for TFT, channel regions 13, 14 for TFT and node capacity forming regions 14', 14'a are formed on the TFT active layer polysilicon 11, 11a. The source region 12 for TFT to be connected with a power supply is located in the center of a memory cell and arranged in the direction of the short side of memory cell. With such arrangement, the required area can be reduced and the effective overlapped part between the drain region 14 for TFT and a ground line 7 can be increased.
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Inventors:
Makoto Kitakata
Application Number:
JP4021195A
Publication Date:
December 10, 1997
Filing Date:
February 28, 1995
Export Citation:
Assignee:
NEC
International Classes:
H01L27/04; H01L21/822; H01L21/8244; H01L27/11; H01L29/786; (IPC1-7): H01L21/8244; H01L27/11
Domestic Patent References:
| JP482264A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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