Title:
STATIC RAM
Document Type and Number:
Japanese Patent JPS6028096
Kind Code:
A
Abstract:
PURPOSE: To attain a large memory capacity with high-speed operation and small power consumption by constituting a memory cell with a latch circuit and using a differential bipolar FET to a sense amplifier.
CONSTITUTION: The memory cell MC consists of memory MOSFETQ1 and Q2 where a gate and a drain are formed alternately into a latch form and high resistances R1 and R2 made of polysilicon layers. While a sense amplifier consists of differential bipolar transistors TRT5 and T6. Then the memory cell reading voltages emerging at common data lines CD and -CD are supplied to the bases of the TRT5 and T6. The collector outputs of the TRT5 and T6 are transmitted to a data output buffer DOB through emitter follower TRT7 and T8.
Inventors:
ODAKA MASANORI
MIYAOKA SHIYUUICHI
IKEO HARUYUKI
TANBA NOBUO
OGIUE KATSUMI
MIYAOKA SHIYUUICHI
IKEO HARUYUKI
TANBA NOBUO
OGIUE KATSUMI
Application Number:
JP13581283A
Publication Date:
February 13, 1985
Filing Date:
July 27, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C11/419; G11C11/34; (IPC1-7): G11C7/06
Domestic Patent References:
| JPS55129994A | 1980-10-08 | |||
| JPS55146678A | 1980-11-15 | |||
| JPS56107385A | 1981-08-26 |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)