PURPOSE: To attain high speed operation by generating an equalized pulse from the output signal of a write amplifier by the unit of either a memory block or a memory mat, and equalizing a complementary data line combined with a memory cell.

CONSTITUTION: Both a write recovery pulse WRP and an inside write control signal WE1 are formed by the output signal of a write amplifier WA correspond ing to either the plural divided memory blocks or the plural divided memory mats, by the unit of the memory block to be written in. Because of this, the number of the fan out of a pulse WRP generating circuit can be decreased, and the most effective complementary data line can be equalized. And also, the pulse WRP and a signal WE1 are supplied according to the common comple mentary data line, that is, the amplifier WA, and limited to the unit of the memory block to be written in by the output signal of the amplifier WA, in order to prepare each of the pulse WRP and the signal WE1. Because of this, a timing margin such as the write pulse or the recovery pulse can be reduced. Thus, the high speed operation can be attained.