Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
STATUS SIGNAL DETECTOR
Document Type and Number:
Japanese Patent JPH0335341
Kind Code:
A
Abstract:

PURPOSE: To improve the processing efficiency of a CPU by setting a status signal detector consisting of a latch circuit and a comparator between an I/O port and the CPU.

CONSTITUTION: A status signal detector 4 detects the abnormality of a status signal 7 showing the working state of an external peripheral device 1 which transmits data. The detector 4 contains a latch circuit 5 which receives and latches the signal 7 of the device 1 via an I/O port 2 to hold the signal 7 until the next signal 7 is received and outputs the held signal 7 as a comparison status signal 8. Furthermore a comparator 6 is added to the device 1 to compare the signal 8 received from the circuit 5 with the signal 7 of the device 1 and outputs a generated interruption signal 9 to a CPU 3 at detection of the abnormality. Thus the processing efficiency of the CPU is improved.


Inventors:
MORIKAWA TORU
Application Number:
JP17008389A
Publication Date:
February 15, 1991
Filing Date:
June 30, 1989
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G06F11/30; G06F13/00; (IPC1-7): G06F11/30; G06F13/00
Domestic Patent References:
JPS5061153A1975-05-26
JPS5425708A1979-02-26
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)