Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP3200863
Kind Code:
B2
Abstract:
PURPOSE:To reduce the OFF current of an insulated gate type field effect transistor by a method wherein a fluorine content in a polycrystalline semiconductor layer is controlled to be not higher than 1X10<18>/cm<3>. CONSTITUTION:A polycrystalline semiconductor layer 109 mainly made of silicon is formed on an insulating layer 107 which is to be a gate insulating film. The polycrystalline semiconductor layer 109 is formed by a plasma CVD method with mixed gas composed of monosilane, disilane, trisilane or the like and hydrogen gas with a ratio of 1:20-1:200 as reactive gas. Then fluorine ions are implanted as impurities to form source/drain regions 110. The source/drain regions 110 formed by ion implantation are activated by annealing. A fluorine content in the polycrystalline semiconductor layer 109 is so controlled as to be not higher than 1X10<18>/cm<3>. It is to be noted that the annealing treatment for the activation is performed in a plurality of times with different temperatures respectively. With this constitution, the OFF current of an insulated gate type field effect transistor can be reduced.
Inventors:
Hideaki Oka
Application Number:
JP9211991A
Publication Date:
August 20, 2001
Filing Date:
April 23, 1991
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L21/205; H01L21/336; H01L21/84; H01L29/78; H01L29/786; (IPC1-7): H01L29/786; H01L21/205; H01L21/336
Domestic Patent References:
| JP1270310A | ||||
| JP56135968A | ||||
| JP5294080A | ||||
| JP6245179A |
Attorney, Agent or Firm:
Kisaburo Suzuki (1 outside)