Title:
STEP TYPE MEMORY SEQUENCER
Document Type and Number:
Japanese Patent JPS5752905
Kind Code:
A
Abstract:
PURPOSE:To freely change the order of selection of input, by writing in the input selection signal of a multiplexer in a memory and selecting the advancement signal with a desired order with the multiplexer. CONSTITUTION:The output of a latch circuit latching the output of a memory 4 is divided into two parts. The 1st output is an address signal of a memory 6 and the data written in the memory is transmitted to a control objective via an output conversion circuit 7. The 2nd output is transmitted to a multiplexer 2 and selects the input signal inputted via an input conversion circuit 1. When a selected signal is inputted, a clock generating circuit 3 outputs a clock and an advance signal, and the next data to the memory 4 is applied to a latch circuit 5 and advances the sequence.
Inventors:
OGAWA MASANOBU
MASUO YASUO
MASUO YASUO
Application Number:
JP12680480A
Publication Date:
March 29, 1982
Filing Date:
September 12, 1980
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS LTD
International Classes:
G05B19/05; G05B19/045; (IPC1-7): G05B19/02
Domestic Patent References:
| JPS52144580A | 1977-12-01 |