PURPOSE: To attain simplified bus line connection by reading out a storage unit at the time of the inherent identification information of the storage unit out of respective storage units connected to a common bus coincides with information specified by a processing system.
CONSTITUTION: When a selector code consisting of 3 bits received from an address bus 12 coincides with an expansion signal of 8 address lines 38, a data selector 30 energizes a cartridge selected line 28. Consequently, ROM/RAM cartridges 20 up to 8 units can be connected to the same bus system 16. Inherent numbers are assigned to respective cartridges 20 and identification information is set up in respective data selectors 30 from a CPU 10. At the time of reading/ writing data from in the cartridges 20, the CPU 10 outputs an address to address lines 12a, 12b in the address bus 12.
Next Patent: MEMORY CONTROL SYSTEM