MEMORY DEVICE

Japanese Patent JP2023032445

A

To provide a memory device capable of suppressing data writing in a memory cell not to be written in a write operation.SOLUTION: A memory device includes: a memory cell array in which memory strings including a plurality of memory cells in which a cell transistor associated with a first potential applying electrode and a resistance change memory region are connected in parallel are arrayed; and a potential setting circuit for setting a potential of the first potential applying electrode. In the potential setting circuit, a potential of the first potential applying electrode of the memory cell not to be written to a potential at which the cell transistor maintains an ON state in a write operation before setting the first potential applying electrode of the memory cell to be written to a potential at which the cell transistor becomes an OFF state. In the potential setting circuit, a potential of the first potential applying electrode of the memory cell not to be written is set to a potential before the write operation, after setting the first potential applying electrode of the memory cell to be written to a potential at which the cell transistor becomes an ON state.SELECTED DRAWING: Figure 1

SHIGA HIDEHIRO
TAKASHIMA DAIZABURO

JP2021138579A

March 09, 2023

August 27, 2021

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KIOXIA CORP

G11C13/00; H01L21/336; H10B43/27; H10B63/10

Hidekazu Miyoshi
Shunichi Takahashi
Masakazu Ito
Toshio Takamatsu

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