Title:
記憶装置
Document Type and Number:
Japanese Patent JP4666008
Kind Code:
B2
Abstract:
The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
Inventors:
Satoru Hanzawa
Kiyoshi Ito
Hideyuki Matsuoka
Motoyasu Terao
Ken Sakata
Kiyoshi Ito
Hideyuki Matsuoka
Motoyasu Terao
Ken Sakata
Application Number:
JP2008148726A
Publication Date:
April 06, 2011
Filing Date:
June 06, 2008
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L27/105; G11C11/15; G11C11/16; G11C13/00; G11C13/02; G11C16/02; H01L21/8246; H01L27/10; H01L27/24; H01L45/00
Domestic Patent References:
| JP6037279A | ||||
| JP2002009366A | ||||
| JP2003218326A | ||||
| JP2002343077A |
Foreign References:
| WO2000057498A1 |
Attorney, Agent or Firm:
Manabu Inoue