Title:
集積回路用コンデンサの構造およびその製造方法
Document Type and Number:
Japanese Patent JP3627814
Kind Code:
B2
Abstract:
A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography. The method provides a capacitor of a simple, compact structure which may be integrated with CMOS, Bipolar and Bipolar CMOS processes for submicron VLSI and ULSI integrated circuits.
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Inventors:
Emesh Ismail Tea
Calder Ein Dee
Hove Q
Jolly garwinder
Madsen Lynette Dee
Calder Ein Dee
Hove Q
Jolly garwinder
Madsen Lynette Dee
Application Number:
JP50945995A
Publication Date:
March 09, 2005
Filing Date:
September 20, 1994
Export Citation:
Assignee:
NORTEL NETWORKS LIMITED
Macmaster University
Macmaster University
International Classes:
H01L21/8247; H01L21/02; H01L21/822; H01L21/8242; H01L21/8246; H01L27/04; H01L27/10; H01L27/105; H01L27/108; H01L29/788; H01L29/792; (IPC1-7): H01L21/8242; H01L21/822; H01L27/04; H01L27/105; H01L27/108
Domestic Patent References:
| JP4082266A | ||||
| JP4266062A | ||||
| JP7099290A | ||||
| JP2186629A | ||||
| JP3076262A | ||||
| JP5343617A | ||||
| JP6314768A |
Attorney, Agent or Firm:
Kazuto Izumi