STRUCTURE FOR MOUNTING SEMICONDUCTOR CHIP

Title:

STRUCTURE FOR MOUNTING SEMICONDUCTOR CHIP

Document Type and Number:

Japanese Patent JP3704864

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To prevent a reinforcing resin from being peeled from wirings in the parts of the wirings to inspection lands.
SOLUTION: The mounting structure, which is constituted by injecting a reinforcing resin 9 between a flip chip IC 7 and an aluminium laminated board 1, of the flip chip IC 7 is constituted into such a structure that inspection lands 6, which are used for an inspection of the chip IC 7, by-pass the fillet parts A of the resin 9 by vias 2 and internal layer wirings 3, which are formed in the board 1, and are electrically connected with conductor lands 4.

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Inventors:

Asai Yasutomi
Shinji Ota
Takashi Nagasaka

Application Number:

JP2808797A

Publication Date:

October 12, 2005

Filing Date:

February 12, 1997

Export Citation:

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Assignee:

株式会社デンソー

International Classes:

G01R31/28; H01L21/66; H01L23/12; H01L23/13; H01L23/28; H01L21/60; H01L23/498; (IPC1-7): H01L23/13; G01R31/28; H01L21/60; H01L23/12; H01L23/28

Domestic Patent References:

JP10092878A
JP8255976A
JP8162499A
JP341757A

Attorney, Agent or Firm:

Hirohiko Usui
Daito Kato
Takashi Ito

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