Title:
STRUCTURE OF PLASMA DISPLAY PANEL AND METHOD OF DRIVING THE SAME
Document Type and Number:
Japanese Patent JP3523180
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To manufacture a plasma display panel of high resolution that enables to reduce a width of address pulses by increasing the quantity of priming particles in a discharge cell and reducing the discharge delay phenomenon of an address discharge.
SOLUTION: This plasma display panel comprises a plurality pairs of hold electrodes being continuously formed on a substrate, a plurality of common electrodes of which one to a hold electrode pair is formed therebetween, and a dielectric layer being formed on the substrate to coat the hold electrodes and the common electrodes, and also the plasma display panel is formed by steps of applying common pulses that are turned on/off periodically to the common electrodes, applying scan pulses to any one of a pair of hole electrodes, and applying address pulses to address electrodes when the scan pulses applied to any one of a pair of electrodes, wherein since there is improved discharge condition within the discharge cell, the discharge delay can be reduced in comparison with a prior art.
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Inventors:
Jin, Yon Kim
Son, Hoo Kan
Son, Hoo Kan
Application Number:
JP2000331084A
Publication Date:
April 26, 2004
Filing Date:
October 30, 2000
Export Citation:
Assignee:
LG ELECTRONICS INC
International Classes:
G09F9/313; G09G3/20; G09G3/288; G09G3/291; G09G3/293; G09G3/294; G09G3/298; H01J11/12; H01J11/14; H01J11/22; H01J11/24; H01J11/26; H01J11/28; H01J11/32; H01J11/34; H01J11/38; H01J11/44; (IPC1-7): H01J11/00; G09F9/313; G09G3/20; G09G3/28; H01J11/02
Attorney, Agent or Firm:
山川 政樹