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Patent Searching and Data


Title:
SUPERCONDUCTION DELAY LINE MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS6139996
Kind Code:
A
Abstract:

PURPOSE: To enlarge delay time per unit wiring length at a delay line part by prescribing a dielectric constant of an insulation layer between a superconduction transmission line for a delay line and an earth plate.

CONSTITUTION: When a dielectric constant of an insulation layer 3 between a superconduction transmission line 4 for a delay line connected through a peripheral circuit including a signal line 10 and a Josephson junction film 3 and an earth plate 2 is larger than a dielectric constant of insulators 5, 9, 11, etc., between the peripheral circuit and the line 4. The delay time per unit wiring length in proportion to a square root, etc. of the dielectric constant becomes smaller than the delay time at the wiring of the peripheral circuit part. As this result, repeated frequency of the signal can be enhanced, writing and reading can be executed at the high frequency and a superconduction delay line memory device with large memory capacity can be obtained.


Inventors:
NAGAI HAJIME
Application Number:
JP16049584A
Publication Date:
February 26, 1986
Filing Date:
July 31, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
G11C21/00; G11C11/44; H01L39/22; (IPC1-7): G11C11/44; G11C21/00
Attorney, Agent or Firm:
Uchihara Shin