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Title:
SUPERVISING CONTROLLER
Document Type and Number:
Japanese Patent JPH0329432
Kind Code:
A
Abstract:

PURPOSE: To suppress the increase in the circuit scale and to display newest supervisory information in a short time without increase of a load for a control MPU by reading the content of a display memory whose address is made coincident with that of a work memory to display the information onto a display panel.

CONSTITUTION: Addresses of control MPU 1 for a display memory 6 are made coincident with addresses of the control MPU 1 on a bus storing alarm status information (supervisory information) collecting by the control MPU 1 from other supervisory stations and a supervisory controller of its own station for a work memory 2 used by the control MPU 1. Then a control circuit 8 supervises the address bus of the control MPU 1, and when the control MPU 1 collects the alarm status information (monitor information) and stores it in the work memory 2, the readout from the display memory 6 is stopped to revise the display. Thus, the newest supervisory information is displayed in a short time without increasing the load of the control MPU 1 and the increase in the circuit scale is suppressed.


Inventors:
TANABE NAOTO
Application Number:
JP16308689A
Publication Date:
February 07, 1991
Filing Date:
June 26, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G08B23/00; G08B25/00; H04B17/00; H04Q9/00; (IPC1-7): G08B23/00; H04B17/00; H04Q9/00
Attorney, Agent or Firm:
Akira Yamatani



 
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