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Title:
SUPPRESSING CIRCUIT OF UNDESIRED WAVE
Document Type and Number:
Japanese Patent JPS56112126
Kind Code:
A
Abstract:

PURPOSE: To exactly suppress an undesired wave, by leading a lock signal of the PLL circuit to the switching circuit containing a time constant circuit, and controlling the transmission system of a radio set.

CONSTITUTION: The unlock signal of H level which is generated on the pull-in time until the PLL circuit is locked, is charged to the capacitor C0 through the diode D0. Since this charging time constant is small, a small unlock signal is also approved. When the unlock signal exists, the potential at the base of the transistor Q0 is high, and it is conducting. When the unlock signal has stopped, the cpacitor C0 discharges. Since this discharging time constant is large, the transistor Q0 becomes nonconducting after a while. When the transistor Q0 has become nonconducting, the capacitor starts to charge, the voltage at the base of the transistor Q1 is also raised gradually, the transistor Q1 starts its operation, and a signal is made to pass through to the output (4) from the input (3).


Inventors:
AKIMOTO TAKENAGA
Application Number:
JP1484580A
Publication Date:
September 04, 1981
Filing Date:
February 12, 1980
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H04B1/04; H03L7/08; (IPC1-7): H03L7/06; H04B1/04
Domestic Patent References:
JPS538007A1978-01-25



 
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