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Patent Searching and Data


Title:
SWITCH GATE CIRCUIT CONVERTER
Document Type and Number:
Japanese Patent JPH02232743
Kind Code:
A
Abstract:

PURPOSE: To prevent the occurrence of malfunction at the time of logic simulation of a circuit having plural switch gates connected in series by providing a circuit data input part, tristate gates, wired dots, etc.

CONSTITUTION: When a signal having a signal strength F and signal value '1' is inputted to input terminals 1, 2, and 13, tristate gates 9, 10, 11, and 12 are turned on, and this signal is propagated to all circuits. When events simultaneously occur in terminals 1 and 2 and signals of terminals 1 and 2 go to Z, the output signal Z of a buffer 5 is propagated to gates 9 and 10 and wired dots 14 and 15. The output signal Z of a buffer 6 is propagated to tristate gates 12 and 11 and dots 14 and 15. Therefore, output signals of dots 14 and 15 go to Z, and the signal Z to be essentially propagated is propagated to output terminals 3 and 4. Thus, the malfunction is prevented at the time of simulation of the circuit having plural switch gates (tristate gates) connected in series.


Inventors:
FUJITA TAKESHI
MASUDA YASUO
MURAOKA MICHIAKI
Application Number:
JP5404089A
Publication Date:
September 14, 1990
Filing Date:
March 07, 1989
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G01R31/28; G06F11/26; G06F17/50; G06F11/25; H01L21/82; H03K19/0175; (IPC1-7): G06F11/26; H01L21/82; H03K19/0175
Attorney, Agent or Firm:
Shigetaka Awano (1 person outside)