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Title:
SWITCH SWITCHING LOGICAL VALUE LATCH CIRCUIT
Document Type and Number:
Japanese Patent JPS55140328
Kind Code:
A
Abstract:

PURPOSE: To obtain a latch circuit which switches a switch in a high speed and prevents malfunctions of the switch, by providing an integral input type FF in the circuit which holds the logical value of the switching signal for the switch having a mechanical contact.

CONSTITUTION: Time constant circuit T11 consisting of resistances R11 and R12 and capacitor C11 is connected to switch SW11 having a mechanical contact, and trigger pulse generator T12 and T-type FF T13 are connected to circuit T11 in order. FF T13 is provided with resistances R13 and R14 of integral time constant t2 and capacitors C12 and C13, and is equipped with trigger pulse stopping diodes D11 and D12. In case that chuttering or noise shorter than time constant t2 is included in trigger pulses, NANd gates N1 and N2 discriminate this case as a case, where the input logic in not changed, without exceeding the threshold voltage, and the output logic is not inverted. Consequently, FF T13 can be prevented from malfunctions dependent upon noise, and the release time of circuit T11 can be shortened, and switch SW11 can be switched rapidly.


Inventors:
MIYAZAKI HIROYUKI
Application Number:
JP4823579A
Publication Date:
November 01, 1980
Filing Date:
April 18, 1979
Export Citation:
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Assignee:
NIPPON HAMONDO KK
International Classes:
H03K3/037; H03K5/1254; (IPC1-7): H03K5/01; H03K19/00



 
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