Title:
SWITCHED CAPACITOR CIRCUIT
Document Type and Number:
Japanese Patent JP3132064
Kind Code:
B2
Abstract:
PURPOSE: To reduce the sampling noise without using a low pass filter.
CONSTITUTION: A switched capacitor integrator is provided with a capacitor 1, C-MOS analog switches 2 to 5, an operational amplifier 6, and an integrating capacitor 7. Two pairs of C-MOS transistors are connected in parallel to constitute each of C-MOS analog switches 2 to 5. A timing generating circuit 11 takes a clock pulse as the input and slightly delays and outputs the rise timing of a turning-on signal to successively turn on C-MOS transistors of C-MOS analog switches 2 to 5.
More Like This:
| WO/1995/013655 | METHOD AND APPARATUS FOR DETECTING AN INPUT SIGNAL LEVEL |
| JPS63171014 | SWITCHED CAPACITOR CIRCUIT |
Inventors:
Tetsuo Hirano
Application Number:
JP19450591A
Publication Date:
February 05, 2001
Filing Date:
August 02, 1991
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H03H19/00; G06G7/186; (IPC1-7): H03H19/00
Domestic Patent References:
| JP6327114A | ||||
| JP6449311A | ||||
| JP57141420U |
Other References:
１９９１年電子情報通信学会秋季大会講演論文集〔分冊５〕（１９９１年９月５日〜８日）ｐ．５−１２４
Attorney, Agent or Firm:
Hironobu Onda