PURPOSE: To improve the amplitude distortion and phase distortion by increasing the ratio of an input sampling time out of the input sampling time and a holding time in one period of a capacitor circuit using a factor multiplying circuit.

CONSTITUTION: In this invention, the ratio of the input sampling time TS to the holding time TH is changed, i.e. the input sampling time TS is increased as large as possible as compared with the holding time TH. If the input sampling time TS is set up to a long period within the range that the movement of the charge of capacitors C1, C2 and the setting of an operational amplifier OA will have been completed, the following time of the output to -C1/C2 times the input is expanded, so that the distortion can be improved. Thus, the amplitude distortion and phase distortion can be improved only by changing the driving timing of the switch in the switched capacitor circuit and the circuit can be widely applied to a factor multiplying circuit requiring high accuracy since said improvement can be attained easily by a general logical circuit.