PURPOSE: To decrease element sensitivity by providing a switched capacitor HPF circuit in which a quartic LC ladder type HPF is simulated.
CONSTITUTION: The sampling frequency and cutoff frequency of the switched capacitor type HPF circuit in which the quartic LC ladder type HPF shown in a figure (a) is simulated as shown in a figure (b) are denoted as fS and fC. In this case, we have C11/C10=1+1/R0, C12/C10=1, C13/C10=(C1+C2)/ C1C2fS, C14/C10=1, C15/C10=1/C1fS, C21/C20=1/L1fS, C31/C30=1/R0, C32/C30=1/L2fS, C41/C40=1, C42/ C40=1/C2fS, and C43/C40=1/C3fS, where C is the capacity value of the capacitor, R is the resistance value of a resistance, and L is the inductance value of a coil. Then, the element sensitivity of the LC ladder type circuit (a) is low as known, so the sensitivity fS/fC of the element in the figure (b) wherein it is simulated is low.
HABUKA RIYUUJI
KIMURA TADAKATSU
NIPPON TELEGRAPH & TELEPHONE