PURPOSE: To suppress the reduction of processing speed of the whole system at its minimum by using a frequency dividing circuit switching a clock from a microprocessor chip to 1/2 frequency only when a specific peripheral IC is selected.

CONSTITUTION: A microprocessor 1 outputs an address of an input port 3 to a bus AB and an address decoder 2 inputs a selecting signal to the CS input of the port 3. Subsequently, the microprocessor 1 outputs a read enable signal to the port 3 and a NOR gate 4. When the read enable signal is turned to the L level, the output of the gate 4 is turned to H. When the K input of an FF6 is on the H level, the FF6 outputs a signal obtained by dividing the output frequency of an oscillator 5 into 1/2 from its Q output, and when the K input is on the L level, it outputs always a H level signal. When the Q output of the FF6 is on the H level, the FF7 outputs a signal to be inverted by the decay of the output of the oscillator as its Q output. During the period when the output of the gate 4 is on the L level, the clock frequency of the processor 1 is a half of the H level frequency.