To provide a synchronization circuit by which an initial synchronizing signal is locked at a high speed while reducing the power consumption and the circuit scale.

In a synchronization circuit, a correlation device 11 and a level detection section 12 calculate an amplitude or a power value being a scalar value from a correlation value between a reception signal for each sample and a spread code, an averaging section 13 calculates a mean value of accumulated results corresponding to the scalar value and the sample, a DPRAM 14 generates an averaged delay profile, a path detection section 15 retrieves a peak from the averaged delay profile, the position of the peak is outputted as a latch timing, a DPLL 16 detects a deviation between the latch timing of the maximum peak and the timing of the spread code for reception to fine- adjust the output timing of the spread code so as to cancel the deviation.