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Title:
SYNCHRONIZATION CONTROL CIRCUIT, SEMICONDUCTOR DEVICE AND CONTROL METHOD
Document Type and Number:
Japanese Patent JP2010056888
Kind Code:
A
Abstract:

To provide a synchronization control circuit capable of further reducing an area or power consumption in comparison with conventional circuits.

In a frequency divider circuit unit 26, a frequency-divided clock RSELO is generated by frequency-dividing an internal clock LCLK whose phase is advanced with respect to an external clock, and a delayed frequency-divided clock RSELI is generated by delaying the frequency-divided clock RSELO. A signal fetched from the outside synchronously to an internal clock PCLK, whose phase is delayed with respect to the external clock, is held in a latch circuit 22 synchronously to the delayed phase-divided clock RSELI. Next, an output signal of the latch circuit 22 is read into a latch circuit 23 synchronously to the frequency-divided clock RSELO and outputted as a signal synchronized to the internal clock LCLK. Then, the frequency divider circuit unit 26 comprises a variable frequency divider circuit 24 that frequency-divides the internal clock LCLK with a predetermined variable frequency dividing number.


Inventors:
SHIBATA TOMOYUKI
Application Number:
JP2008219744A
Publication Date:
March 11, 2010
Filing Date:
August 28, 2008
Export Citation:
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Assignee:
ELPIDA MEMORY INC
International Classes:
H03L7/06; H03K5/00; H03K23/64; H03L7/00
Domestic Patent References:
JP2000332732A2000-11-30
JP2001306176A2001-11-02
JP2004192791A2004-07-08
JPH0934585A1997-02-07
JP2007087468A2007-04-05
JPH07274257A1995-10-20
JP2004258888A2004-09-16
JPH02228759A1990-09-11
JPH10200516A1998-07-31
JPH04336825A1992-11-25
JP2007115307A2007-05-10
JP2000332732A2000-11-30
JP2001306176A2001-11-02
JP2004192791A2004-07-08
JPH0934585A1997-02-07
Attorney, Agent or Firm:
Sumio Tanai
Tadashi Takahashi
Naoki Ofusa
Kazunori Onami



 
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