Title:
SYNCHRONIZATION METHOD AND CIRCUIT LAYOUT FOR EXECUTING THE SAME
Document Type and Number:
Japanese Patent JP3423013
Kind Code:
B2
Abstract:
PURPOSE: To reduce the possibility of synchronization, having an error by determining the temporary position of inserted synchronizing sequence in comparison with the prescribed bit sequence of synchronizing sequence.
CONSTITUTION: A magnetic tape 1 takes out a digital signal, recorded by a magnetic reproducing head 2. When synchronizing the run length - limitation (1.7)-code of 2/3 code ratio, so as to insert the prescribed synchronizing bit sequence into the data stream of code words, corresponding the phase correcting decoding of code for the width of 3 bits, the synchronizing sequence provided with three sequential code words for the width of 3 bits at least is generated as the synchronizing bit sequence to be inserted. This sequence has six values '0' between two values '1' at least, the temporary position of inserted synchronizing sequence is specified by determining the number of values '0' between two values '1', so that the word limitation of serially transmitted code words is recognized.
Inventors:
Ewald Felloweri
Wolfram Zielung Gibble
Jens Lehmann
Wolfram Zielung Gibble
Jens Lehmann
Application Number:
JP22291292A
Publication Date:
July 07, 2003
Filing Date:
August 21, 1992
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
G11B20/00; G11B20/14; H03M5/14; H03M7/14; H03M7/46; H04L7/02; H04L25/49; (IPC1-7): H04L7/02; H03M7/14; H04L25/49
Domestic Patent References:
JP5570922A | ||||
JP2243024A | ||||
JP63174430A | ||||
JP62123848A | ||||
JP451615A | ||||
JP61250875A |
Attorney, Agent or Firm:
Kosugi Sugimura (4 others)
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