PURPOSE: To enable to take synchronizm at high speed without any inconvenience even if the circuit element much in delay time is used, by providing the circuit delaying the branched output of the timing generating circuit.

CONSTITUTION: The system provides additionally the gate circuit 10, 2-bit delay circuits 11 (output the timing signal delayed by 2-bit's share with the clock signal) and 12 (output by delaying by 2-bit's share for the received PCM signal A fed at the input terminal Tin with the clock signal). Next, the delayed PCM signal is fed to the decoding section at the reception side via the terminal Tout. Further, the switching circuit 13 is operated with the output E of the out of synchronism status memory 6 (solid lines indicate the normal state). Thus, whether or not the synchronizing signal is present in the PCM signal before (n-1)-bit in advance is discriminated and the operation of determination to be braught to the state of out of synchronism at (n-1)-bit after that can be made, allowing to avoid the necessity to process the full operations within one clock signal time and to make high speed the PCM transmission.