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Title:
SYNCHRONIZING CODE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS62292037
Kind Code:
A
Abstract:

PURPOSE: To detect a synchronizing signal by a few number of constituents, by multiplexing plural input code groups by every bit, and comparing an output after multiplexing, with a prescribed synchronizing signal detecting signal.

CONSTITUTION: Inputted plural input code groups are multiplexed by every bit by a multiplexing circuit 1. The output is compared with the prescribed synchronizing signal detecting signal at the first comparator 2, and also, it is code-converted at a code converter 4. By comparing the sizes of a code- converted conversion signal, and a prescribed conversion signal at the second comparator 6, a specific synchronizing code is outputted from the plural input code groups. Thereby, since the circuit 1 multiplexes the input code group corresponding to synchronizing codes included over entire plural input code groups, the constitution of a detection circuit, etc., can be simplified.


Inventors:
SHIBUYA AKIHIRO
MORIYA YOICHI
Application Number:
JP13674986A
Publication Date:
December 18, 1987
Filing Date:
June 12, 1986
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K5/19; H04J3/06; H04L7/08; H04L7/10; (IPC1-7): H03K5/19; H04J3/06; H04L7/08; H04L7/10
Attorney, Agent or Firm:
Masuo Oiwa