To prevent run out synchronizing by supplying reset signals from the counters of preceding stages, which are outputted from gate circuits, to the clear terminals of the counters of the succeeding stages when the reset signals from the proceeding stages are at the outside of the window signals from the window signal generating circuits and obtaining synchronization in the succeeding stages.

The reset signals Srst from a master counter and the window signal Swind from the window signal generating circuit 6 are supplied to an OR gate 5. Here, when the reset signal Srst is at the outside of the window signal Swind, the reset signal Srst from the master counter, which is outputted from the OR gate, that is, the signal Smrst is supplied to the clear terminal CLS of a slave counter 2 and synchronization is obtained in the slave counter 2 by the master counter 1.