PURPOSE: To discriminate the optimum phase, to reduce the generation of disturbance, and to easily execute conversion to IC, without frequency-dividing a clock pulse, by a delay of an oscillating output and discrimination of the optimum phase by detecting a sampling state due to each delay output.

CONSTITUTION: A clock pulse of a repeating period of 1/2 is generated from an oscillating circuit 32, to a phase synchronizing signal of a repeating signal of a fixed period in a transmitting binary signal, its pulse is delayed by a time of 1/n each of the repeating period, and a clock pulse of (n) phases is generated. By use of this generated pulse, the phase synchronizing signal is sampled for a period of each prescribed bit number, and when its prescribed bit is sampled correctly, an output is generated from detecting circuits 37A∼37H. In accordance with the output of these circuits 37A∼37H, a clock pulse of phase suitable for the binary signal is discriminated from the clock pulse of (n) phases by discriminating circuits 48, 49. Subsequently, by an output of the circuits 48, 49, a pulse of prescribed phases out of the pulse of (n) phases is outputted from a clock pulse selecting circuit 51.