Title:
SYNCHRONIZING SIGNAL DETECTOR
Document Type and Number:
Japanese Patent JP2718600
Kind Code:
B2
Abstract:
PURPOSE: To miniaturize the entire scale of a synchronizing signal detecting circuit by inputting a serial signal being a CD-ROM signal including a synchronizing signal by 16 bit units.
CONSTITUTION: The output of a 16 bit serial register which samples and inputs serial data 101 by a clock signal 102, is converted into parallel data by upper and lower 8 bit serial/parallel converting means 104 and 105 at every upper and lower 8 bits. Then, upper and lower 6 bit serial/parallel converting means 112 and 113 are reset when the synchronizing signal is not valid by the output of a reset signal logical product means 111 which inputs the output signals of upper and lower synchronizing signal validity judging means 106 and 108 which judge the validity of the synchronizing signal from those parallel signals, and the output signal of a word pulse signal means 110. When the synchronizing signal is valid, the output signals of upper and lower logical product means 107 and 108 are sampled by the output signal of the word pulse signal means 110, and the validity of the synchronizing signal is judged by the 6 bit serial/ parallel converting means 112 and 113.
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Inventors:
Fujie Hideki
Application Number:
JP18561692A
Publication Date:
February 25, 1998
Filing Date:
July 14, 1992
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H03M9/00; G06F3/08; H04L7/08; H04N5/93; (IPC1-7): H04L7/08; G06F3/08; H03M9/00; H04N5/93
Domestic Patent References:
| JP1311647A | ||||
| JP440184A |
Attorney, Agent or Firm:
Yoshihiro Morimoto
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