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Patent Searching and Data


Title:
SYNCHRONIZING SIGNAL SEPARATING CIRCUIT FOR TELEVISION SIGNAL
Document Type and Number:
Japanese Patent JPS5860880
Kind Code:
A
Abstract:

PURPOSE: To increase input impedance by providing a bypass circuit consisting of a bias resistance, a diode, and a capacitor between the gate of an MOS inverter of complementary constitution and a source-drain connection point.

CONSTITUTION: An AC-coupled inverter amplifier consists of complementary MOS transistors (TR) 12 and 13, etc. Further, a resistance 18, a diode 19, and a resistance 17 are connected in series between the drain and gate, and at the connection point between the diode 19 and resistance 17, a capacitor 20 forms a bypass. Consequently, a video signal inputted through a capacitor 14 is inverted and amplified by CMOS inverters 12 and 13 to charge the capacitor 20 with the amplified peak voltage of the synchronizing signal side through the diode 19. This charging voltage biases the gate through the resistance 17. Therefore, when the video signal is inputted, the CMOS inverters 12 and 13 bias the synchronizing signal to an active area and the video signal to a cut-off area. Consequently, the synchronizing signal is inverted and outputted to the drain 15.


Inventors:
YAMAGUCHI SHIZUO
Application Number:
JP15903881A
Publication Date:
April 11, 1983
Filing Date:
October 06, 1981
Export Citation:
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Assignee:
CITIZEN WATCH CO LTD
International Classes:
H04N5/08; (IPC1-7): H04N5/08