PURPOSE: To detect a synchronous bit within two frames even in the worst case by leading a signal having a generation polynomial bit to a multiplier/divider and detecting the synchronous bit at the point of time of reception of the final bit of one frame when all remainders are zero.
CONSTITUTION: When a synchronous pattern retrieval condition is established to the 1st demultiplexer, a cyclic remainder reset signal is inputted to a reception shift register 51 and the multiplier/divider 55. When data A, B and C exist prior to the synchronous bit of the inputted data in this case, the data overflows from a reception shift register 51 at the back of one frame. The remainder as the result of division of the overflow value by a generation polynomial (X5+X2+1) (X+1) is cancelled, only the synchronous bit, the data and a check signal are calculated and the remainder is outputted from a remainder register. The output of the remainder register is inputted to a detector 56 to detect the synchronous bit.
KAWABE KOUICHI
AOKI KIYOSHI
MEIDENSHA ELECTRIC MFG CO LTD
| JPS5250102A | 1977-04-21 | |||
| JPS57192148A | 1982-11-26 |
Next Patent: LINE SWITCHING CIRCUIT