PURPOSE: To use a synchronous high-speed counter, which has two-system counters, to sychronize stably the phase slippage between trigger signals, which are generated by the change of the repeat frequency of trigger signals, and oscillated clock signals.

CONSTITUTION: FF 6 is sychronized with trigger signal (clear signal) 3, and counter driving signals 7 and 8 which have phases opposite to each other and are inverted mutually are formed and are inputted to two high-speed counters 9 and 10 respectively and cause counters to perform counting or non-counting of high-speed (oscillated) clock signals alternately. Meanwhile, high-speed clock signal 1 is inputted to clock position control part 2, and control part 2 gives a delay to input high- speed clock signal 1 so that the phase slippage between signal 1 and the trigger signal may be synchronized with the trigger signal of counting conrol, which comes next, by signal 20 having the half period of the trigger signal at each non-counting time of counters 9 and 10, thereby performing counting synchronized completely from the rise time of counters. Outputs 11 and 12 of counters 9 and 10 are selected by selction circuit 13 and are outputted to 14.