Title:
同期処理システム及び半導体集積回路
Document Type and Number:
Japanese Patent JP5431907
Kind Code:
B2
Abstract:
A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.
Inventors:
Daisuke Kadota
Application Number:
JP2009288099A
Publication Date:
March 05, 2014
Filing Date:
December 18, 2009
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H03K5/00; H03K21/38
Domestic Patent References:
| JP63175258U | ||||
| JP8241286A |
Attorney, Agent or Firm:
Motohiko Fujimura
Shigeyuki Nagaoka
Shinji Takano
Shigeyuki Nagaoka
Shinji Takano