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Patent Searching and Data


Title:
SYNCHRONOUS RECOVERY TIME MEASURING CIRCUIT
Document Type and Number:
Japanese Patent JPH03244215
Kind Code:
A
Abstract:

PURPOSE: To make measurement easy and to improve reliability by providing first and second FF circuits and measuring synchronous recovery time by using a count number latched by the first and second FF circuits.

CONSTITUTION: When a switch signal (h) of a parallel input/serial output is set to a parallel input mode, a counter circuit 51 starts counting the number of second clocks (d) at timing, when a control signal Sin(c) comes to '1', and at the timing of the starting edge of an out-of-synchronizing signal, a count number (M) up to such a moment is latched and written into a first FF circuit 52. Similarly, a count number (N) up to the timing of the trailing edge of a signal (e) is latched and written into a second FF circuit 53. Next, the switch signal (h) of the parallel input/serial output is set to a serial output mode and a third clock (i) is added from a personal computer to the first FF circuit 52. Then, the written data latched by the first and second FF circuits 52 and 53 are shifted and the second FF circuit 53 sends out serial data (j) in the order of the count number (N) and the count number (M).


Inventors:
TAKAHASHI YOSHITOSHI
Application Number:
JP4355290A
Publication Date:
October 31, 1991
Filing Date:
February 22, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G04F10/04; H03L7/00; (IPC1-7): G04F10/04; H03L7/00
Attorney, Agent or Firm:
Sadaichi Igita