Title:
SYNCHRONOUS SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3645791
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a synchronous semiconductor memory which can discriminate easily normal/defective condition at the time of dynamic burn-in test by doubling operation speed in a test mode.
SOLUTION: A CLK signal 101 and a CLKB signal 102 being its inversion signal are inputted to a clock generating circuit 1, the circuit generates respectively signals of short pulse based on the rise of both signals, and they are inputted into a signal generating section 2 as an ICLK signal 104 and an ICLKB signal 105. The signal generating section 2 activates an ICLKBK signal 105 as an ICLKB signal 106 in a normal operation mode, and activates the ICLKB signal 105 as an ICLKBT signal 107 in a test mode. The signal generating section 2 inputs a doubled frequency multiplied signal 108 in which the ICLK signal 104 and the ICLKBT signal 107 are synthesized, into a control circuit 10. The control circuit 10 controls the operation of each section of the synchronous semiconductor memory synchronizing with the double frequency multiplied signal 108.
Inventors:
Maeda Kazunori
Application Number:
JP2000158099A
Publication Date:
May 11, 2005
Filing Date:
May 29, 2000
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G01R31/3185; G11C7/10; G11C7/22; G11C11/401; G11C11/407; G11C11/4076; G01R31/28; G11C11/4093; G11C29/06; G11C29/12; G11C29/50; (IPC1-7): G11C29/00; G01R31/28; G01R31/3185; G11C11/401; G11C11/407
Domestic Patent References:
| JP2000090696A | ||||
| JP7244999A | ||||
| JP10003800A | ||||
| JP5019026A |
Attorney, Agent or Firm:
Kiyoshi Inagaki
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