PURPOSE: To improve the data transfer capacity by prefetching an address and a read/write flag in the case a bus request is executed from other bus master, in an insignificant time after an access is started to a storage element.

CONSTITUTION: An address on a memory 13 to which a data transfer request is executed from each bus master 1-5, the channel number for showing the bus master which executes the request, and information for showing one of a read or write access are held in a first in first out(FIFO) register 10 in order of the data transfer request, an input and an output of this FIFO register 10 are controlled by a control circuit 11, and a bus control circuit 12 instructs a bus use permission to each bus master 1-5. That is, in the case a bus request is executed from other bus masters 1-5, in an insignificant time until data can be transmitted and received after an access is started to the memory 13, the time of an address cycle becomes invisible by prefetching an address and a read/write flag.