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Title:
SYSTEM FOR CONTROLLING HISTORY MEMORY
Document Type and Number:
Japanese Patent JPS59180759
Kind Code:
A
Abstract:

PURPOSE: To improve the probability of storing data which cause faults in a history memory, by taking data of prescribed cycles after a noted signal is generated into the history memory.

CONSTITUTION: When the input S1 of an operating circuit 14 which performs the increment of addresses is "1", the operating circuit 14 outputs an output which is prepared by adding "1" to the content of an address register 12 and, since the output becomes the next access address of a history memory 10, the address of the memory 10 is updated and the content of a writing data register 16 is successively written in the addresses of the memory 10. A target 20 is set and sets its Q-output to "1" when a noted signal S0 is inputted and, when it is reset by a signal S2, sets the Q-output to "0". A gate 24 obtains the OR of signals selected by a mode selector 22 and outputs the OR as V and -V. When the V becomes V=1, a (+1) circuit composed of a counter 32 and operator 34 starts adding "1" and, when the contents of the counters 32 and 28 coincide with each other, an output S2 is generated from a comparator 30.


Inventors:
OOYA MASAYUKI
Application Number:
JP5592983A
Publication Date:
October 13, 1984
Filing Date:
March 31, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/34; (IPC1-7): G06F11/34
Domestic Patent References:
JPS5341A1978-01-05
JPS57101955A1982-06-24
Attorney, Agent or Firm:
Fumihiro Hasegawa



 
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