PURPOSE: To update always a reference bit at a high speed, by providing a fetch detecting means which requires reference, on updating means for reference bit, and a register to a storage unit and separately controlling the reference bit updating and data processing.

CONSTITUTION: The address part of an instruction is held in spaces A, B, and C of a register 3 in the order of logical address, address, and real address. An address conversion table 4 holds the logical address and real address as a corresponding table. At a collating circuit 6 it is confirmed that whether a logical address is registered in the table 4 or not. When the collation is made, "1" is inputted into a register 8. The real address is processed in the same way. When the confirmation is good, a register 10 is made to hold "1". The real address is held by a register 9. Upon receiving a read instruction, a detecting circuit 11 inputs "1" into a gate circuit 12. When an address of the table 4 is requested and the request is in reading condition, the circuit 12 brings a register 13 to "1" and inputs the real address into a register 15. The reference bit of a main memory 14 is updated in accordance with the real address and content of the register 13.