PURPOSE: To attain miniaturization of the titled circuit and to improve the reliability by storing a digital signal once in a memory at the pre-stage of a shift register and adding a circuir replacing the sequence and reading n signals in the order of the system 1 to the system N in reading.
CONSTITUTION: An input digital signal is stored once in a memory 6 having an address space of ≥2×(N×n) based on a write address generated through the operation of a counter 7 by the sampling clock frequency. Then an output of the counter 7 is converted by an encoder 8 to generate a read address. Then the digital signal obtained at the shift register 9 having 4-tap output driven by the sampling clock frequency is inputted. Furthermore, data of each output tap is stored in a latch 11 by the clock frequency as the result of frequency division of the sampling clock frequency at a 1/4 frequency division circuit 10. The digital signal is distributed by this operation to attain desired distribution.
UMEMOTO MASUO
KANEDA HIDEHIRO
KATAYAMA HITOSHI
MICHIKAWA YUUICHI
HITACHI ELECTRONICS