Title:
欠陥プリント回路をマッピングするためのシステム
Document Type and Number:
Japanese Patent JP4923180
Kind Code:
B2
Abstract:
A scrap-units-mapping system is disclosed. The system is especially designed for mapping a multi-layers PCB that contains a plurality of PCBs. The disclosed system comprised of an optical inspection system that scans each layer - both sides - of identified layers, that are intended to create a specific PCB, and marks the scrap-units on a layer map; a storage mean to store the layer maps, using any method for storing layers' information; and a combining software that combines the layer maps to create a PCB map, wherein each scrap-unit, which one of its' layers has a defect, is marked. Moreover, the system can further includes an optimization software that matches plurality of layer maps of each terrace-layer of the PCB and define sets of identified layers to join into a PCB with minimum scrap-units, enabling to collect each of the defined sets to join into a PCB.
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Inventors:
Delhi, Neil
Application Number:
JP2007517648A
Publication Date:
April 25, 2012
Filing Date:
June 19, 2005
Export Citation:
Assignee:
Camtek Ltd.
International Classes:
G01N21/956; H05K1/02; H05K3/00; H05K
Domestic Patent References:
| JP2005260112A | 2005-09-22 | |||
| JP2000101253A | 2000-04-07 | |||
| JP2005523493A | 2005-08-04 | |||
| JP2003139720A | 2003-05-14 |
Foreign References:
| WO2003081535A1 | 2003-10-02 |
Attorney, Agent or Firm:
Hitoshi Shinbo
Ikeuchi, Sato & Partners
Ikeuchi, Sato & Partners