To provide a system for locking synchronization of a PLL circuit that can prevent a step change from being caused in a change in a steady-state phase error caused on the occurrence of phase locking of a secondary loop when an input frequency of an input signal to be traced is changed resulting in that production of a wander with a comparatively high frequency can be avoided.

The system for locking synchronization of a PLL circuit that locks a frequency and a phase of an input signal, is provided with analog adder sections 1, 30 that provide an output of a steady phase error obtained by summing the input signal to an inverted output signal as an analog signal, a voltage controlled oscillator section 8 that receives a control voltage to generate an output oscillation signal whose frequency varies with the control voltage and which is outputted to the analog adder sections, integration sections 2, 4, 5, 7 that convert the analog output signal outputted from the analog adder sections, apply integration overtime to the digital signal, and convert the result of integration into an analog signal, and an analog adder section 60 that sums an output of the analog adder sections to an output of the integration sections to generate the control voltage given to the voltage controlled oscillator section.