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Title:
SYSTEM FOR MONITORING TIME SWITCH MEMORY
Document Type and Number:
Japanese Patent JPH0564244
Kind Code:
A
Abstract:

PURPOSE: To always monitor all memory cells inside DM without relying the setting contents of ACM.

CONSTITUTION: An idle time slot address holding circuit 6 selects the one optional time slot of the time slots where the control signal of an address control memory 4 indicates idle so as to hold the address. A timing generating circuit 7 generates a timing signal from address information of the above address holding circuit 6. A word-counter 8 executes counting with the one period of an address counter as one count and generates the address with the word number of a data memory 2 as full count. A selector 9 inputs the output address of the address control memory 4 or the word-counter 8 and selects the address of the word-counter by the timing of the timing generating circuit 7. The data memory 2 is read by the output address so as to monitor all the memory cells.


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Inventors:
YAMASHITA HIROSHI
Application Number:
JP22184191A
Publication Date:
March 12, 1993
Filing Date:
September 02, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04M3/24; H04Q3/52; H04Q11/04; (IPC1-7): H04M3/24; H04Q3/52; H04Q11/04
Attorney, Agent or Firm:
Yosuke Goto (2 outside)