Title:
SYSTEM FOR OPTIMIZED GENERATION OF TEST DATA OF SYSTEM LSI
Document Type and Number:
Japanese Patent JP3737662
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten simulation time and enhance debugging efficiency by efficiently generating the simulation data of a tester without transferring excess data regarding an optimized data generation system to generate data to be used for a test of a system LSI verified in logic simulation at a designing state.
SOLUTION: This system is constituted so as to use only the data of an address used in a logically verified micro program by providing a ROM modeling means to make a verified micro program in the logic simulation into a ROM model, an address tracing means to trace the address of data to be used in execution of the micro program made into the ROM model and a control file generating means to generate a control file for simulation of the test from the traced address.
Inventors:
Kazuyuki Sato
Application Number:
JP34426499A
Publication Date:
January 18, 2006
Filing Date:
December 03, 1999
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F11/22; G01R31/26; G01R31/3183; G06F11/34; (IPC1-7): G06F11/22
Domestic Patent References:
| JP3158971A | ||||
| JP9089999A | ||||
| JP9212383A |
Attorney, Agent or Firm:
Kazuo Hosaka
Fumihiro Hasegawa
Yoshiyoshi Ogasawara
Fumihiro Hasegawa
Yoshiyoshi Ogasawara