PURPOSE: To attain rapid processing by means of a simple constitution by receiving an interruption request generated during the execution of a string instruction on the basis of a level sensing system.

CONSTITUTION: When an interruption sample '0' signal 5 is outputted and a microcondition branch instruction is executed and formed, an interruption sample '0' signal 7 is outputted, and AND gate 12 is validated so as to pass an interruption request signal 4 and a set/reset flip flop (FF) 13 is set up. An output signal 15 from the FF 13 is applied to an OR gate 21 and an OR result between the signal 15 and the request signal 14 is inputted to an AND circuit 10 for detecting an interruption by means of an interruption sample '1' signal 6. Even if the request signal 4 is canceled after outputting the signal 5, an interruption request can be validated and the interruption request based upon the level sensing system can be received. Thus, a microprocessor capable of executing level sensing interruption on the way of execution of an instruction and executing rapid processing and rapid interruption response can be obtained.