Title:
プログラミング動作を最適化することによって推論エンジンを実装するためのシステム及び方法
Document Type and Number:
Japanese Patent JP7116787
Kind Code:
B2
Abstract:
A memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of bit lines each connected to one of the columns of memory cells, and a plurality of differential sense amplifiers each having first and second inputs and an output. For each of the differential sense amplifiers, the differential sense amplifier is configured to generate an output signal on the output having an amplitude that is based upon a difference in signal amplitudes on the first and second inputs, the first input is connected to one of the bit lines, and the second input is connected to another one of the bit lines. Alternately, one or more sense amplifiers are configured to detect signal amplitudes on the bit lines, and the device includes calculation circuitry configured to produce output signals each based upon a difference in signal amplitudes on two of the bit lines.
Inventors:
Tiwari, bipin
Doe, Nan
Doe, Nan
Application Number:
JP2020515179A
Publication Date:
August 10, 2022
Filing Date:
July 03, 2018
Export Citation:
Assignee:
SILICON STORAGE TECHNOLOGY, INC.
International Classes:
G11C16/04; G11C16/34; G11C16/28
Domestic Patent References:
| JP2008077725A | ||||
| JP2001516933A | ||||
| JP2007087441A |
Attorney, Agent or Firm:
Patent Attorney Corporation Wisdom International Patent and Trademark Office
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