強化されたメモリアクセスセキュリティを提供する、メモリに対するデバイスのアクセスを制御するシステムおよび方法

Japanese Patent JP2005512228

A

A host bridge is described including a memory controller and a security check unit. The memory controller is adapted for coupling to a memory storing data arranged within a multiple memory pages. The memory controller receives memory access signals (e.g., during a memory access), and responds to the memory access signals by accessing the memory. The security check unit receives the memory access signals, wherein the memory access signals convey a physical address within a target memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain a security attribute of the target memory page. The security check unit provides the memory access signals to the memory controller dependent upon the security attribute of the target memory page. A computer system is described including a memory storing data arranged within a multiple memory pages, a device operably coupled to the memory and configurable to produce memory access signals, the above described host bridge. The computer system may have, for example, a central processing unit (CPU) including a memory management unit (MMU) operably coupled to the memory and configured to manage the memory. The memory management unit (MMU) may manage the memory such that the memory stores the data arranged within the multiple memory pages. A method is disclosed for providing access security for a memory used to store data arranged within a multiple memory pages.

Jeffrey S. Stronzine
Brian Sea. Burns
Rodney W. Schmidt

JP2003551676A

April 28, 2005

September 12, 2002

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ADVANCED MICRO DEVICES INCORPORATED

G06F12/14; G06F21/24; (IPC1-7): G06F12/14

Masatake Suzuki
Ryota Sano
Yoshito Muramatsu

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